The impetuous development of integrated electronic systems encounters, among others, problems due to the necessary compacting together of sub-systems, circuits, and devices that occasionally may interfere with each other causing malfunctionings of various natures.
In general, electromagnetic compatibility becomes of paramount importance if the effect of disturbances and interferences jeopardizes safety. In certain fields of use of electronic systems such as, for instance, in the automotive industry, aeronautics, biomedics, and the like, electronic devices must be immune to disturbances and at the same time they must not generate noise and disturbances that could affect nearby devices.
The techniques for reducing interference phenomena among distinct electronic devices have become very expensive and they are not always able to meet certain rules of electromagnetic compatibility.
Manufacturers of integrated circuits are pressed to design devices capable of minimizing compatibility problems at the source. In particular, digital devices must generate very little noise, while analog devices must be robust and insensitive as possible to environmental noise.
The “intelligent” part of monolithically integrated systems typically comprises digital circuitry operating with signals of very high frequency, and this is often a source of high-energy noise.
There are different techniques for reducing and confining electromagnetic emissions of an integrated digital circuit. The realization of decoupling filters from supply lines represents the first thing to do for this objective. The simplest decoupling filter consists of a capacitor of relatively large capacitance. This implies the requisite of a commensurate silicon area which notably may become rather costly.
Contrary to the most general design rule, in developing the circuit layouts such to minimize capacitive couplings among different circuit lines (nodes), for the objectives of implementing and effective decoupling from the supply lines, the addressed problem is that of maximizing the capacitive coupling between the two equipotential supply nodes of an integrated circuit while minimizing the silicon area to be spent to this end.
Often, digital devices have numerous input/output (I/O) structures normally realized along the whole or part of the perimeter of the chip by replicating a typical definition module for an I/O interface by the number of input/output pads. Such a definition module is substantially composed of two distinct portions:                1) a portion for defining the I/O circuitry to be realized that commonly comprises the driver, the pre-driver and the control logic of the output stage, eventual Schmitt triggers, and the relative logic control circuitry of the input stage;        2) a portion for defining the supply lines that comprise (at least) two distinct and relatively wide segments of metal rails for the supply (i.e., equipotential nodes VDD and VSS, respectively).        
The two segments of supply lines of each module (that is of the definition mask of the relative metal) relative to an input/output circuit or cell concur to modularly compose perimetral supply rings. Obviously, at locations where the realization of an I/O cell is not contemplated, the definition module (or more precisely, only the portion of it for defining the metal patterning mask) called “filler cell”, will define only segments of the supply lines.
Modern fabrication processes contemplate numerous levels of metallization (up to six/seven levels according to the most recent fabrication technologies), and only the first two levels are in general used to interconnect the circuitry, while the other metals are dedicated to the distribution of the supply voltages to ensure a substantial equipotentiality of the supply node even in presence of large current absorptions.
In particular, the two segments of supply lines of the numerous I/O cells and of eventual filler cells are parallel to each other and all the respective levels of similarly patterned metals overlay one another and are connected together to ensure as much as possible equipotentiality of the so constituted multilayered supply nodes. FIG. 1 depicts such a multilayer metallization structure of such supply rings of an integrated circuit.
FIG. 1 depicts the structure of supply and ground (or negative supply) metallizations according to a fabrication technology that contemplates the presence of up to six metal levels: the four top levels being exploited for distributing the supply to the various functional circuits that are integrated on the chip.
Accordingly, at least along the perimeter of the chip, where the I/O interface cells are integrated, four (or more) superposed metals are interconnected, to constitute a first supply node (VDD) and as many metals are interconnected to constitute a second or virtual ground node (VSS).
Such a modular multilayer metal structure is replicated tens or hundreds of times in an integrated device, often along all four sides of the chip. By placing the modules (I/O and/or filler cell) side by side, multilayer metal rings are realized: one for VDD and one for VSS.
If I/O cells must be realized at regular intervals along each side of the integrated device and not adjacently with neighboring cells (for example, because of assembling requirements in a particular package or because the number of I/O circuits, and, thus, the number of definition modules to be replicated is not large enough to cover the full length of a side of the chip), cells of pure interconnection (filler-cells) that do not include any circuitry, but consists only of segments of metallization lines are defined such to ensure continuity of the two (or more) supply rings.
FIG. 2 depicts a typical layout of I/O modules and/or “filler cells”.
The capacitance between the so constituted parallel lines of VDD and VSS, even if both are realized in the form of a multilayer, is not particularly high because the capacitive coupling is low. Such a structure of parallel metal planes interconnected together even if well suited to satisfy the low impedance requisite of the supply lines (i.e., equipotentiality of the two nodes), does not contribute to constitute an effective decoupling filter of the noise generated by the high frequency switchings of the digital circuits and in particular of the I/O circuits, which must be done by integrating dedicated circuit means.
Moreover, the typical multilayer structure of the supply rings of the I/O circuits illustrated in FIGS. 1 and 2 precludes any possibility of using the silicon area occupied by these multilayered supply lines for other purposes, such as, for realizing decoupling capacitors. On the other hand, this area is not negligible because the width of the supply rails must be commensurate to support a current of hundreds of milliamperes or even a current of few amperes during peaks of power absorption, for instance, at switchings of the logic circuits.
The ever increasing cost that is attributed to the unity of silicon area calls for structures that, whenever possible, besides providing the functionality for which they are realized, allow exploitation of the same integration area also for other objectives for reducing costs.